Posts Tagged ‘Magma’

HDL Design House Adopts Magma’s Full Suite of Software to Accelerate SoC and IP Development

March 31st, 2011

Magma Design Automation Inc. (Nasdaq: LAVA), a provider of chip design software, and HDL Design House, creators of re-usable IP cores, verification components and behavioral simulation models, today announced that HDL Design House has adopted the full suite of Magma chip design software, including the Talus® digital IC implementation system and the Titan™ mixed-signal design platform. With Magma as its primary EDA vendor, HDL Design House will now be able to provide its clients with complete mixed-signal system on chip (SoC) design services, and be able to augment their current family of soft digital IP cores with analog IP. Its proven technology leadership was crucial in HDL Design House’s decision to standardize on Magma’s digital and analog implementation, simulation, and verification and characterization software.

“Our customers range from small start-up companies to multi-national corporations in the semiconductor, wireless and medical industries and have varying design requirements,” said Predrag Markovic, president and CEO, HDL Design House. “With Magma’s full suite of design software, we can accelerate the delivery of our portfolio of design IP, and meet our customers’ varying requirements with a combination of world class expertise in, and best-in-class tools for, digital and analog design, verification and characterization.”
“Magma offers a broad portfolio of leading-edge technology that solves designers’ toughest problems,” said Premal Buch, general manager of Magma’s Design Implementation Business Unit. “By providing advanced capabilities, fast performance and high levels of automation, Magma provides HDL Design House with comprehensive solutions that deliver outstanding quality of results and faster turnaround time.”

Magma: “Fastest Path to Silicon”™
Offering a truly integrated IC design system and highly automated flow, Magma provides designers with the “Fastest Path to Silicon.” The Talus digital implementation system combines traditionally separate front-end and back-end chip design into an integrated flow that’s designed to eliminate iterations between the synthesis and place-and-route processes, accelerate the design cycle and reduce IC development costs. The Titan environment includes the comprehensive Titan Mixed-Signal Design Platform, and the Titan Accelerators, a set of breakthrough point-tool technologies that integrate with and augment existing analog/mixed-signal design flows. The Titan Accelerators provide unique capabilities that dramatically improve analog design productivity, and enable true analog design reuse. Unlike legacy flows, the Titan Accelerators are next-generation design technologies that provide capabilities for rapidly designing, analyzing and optimizing circuit designs and layouts, and implementing them in today’s advanced process geometries. The Titan Mixed-Signal Design Platform tightly integrates mixed-signal implementation with digital implementation, circuit simulation, transistor-level extraction and verification – providing a quantum leap in efficiency and productivity for analog designers.

Source:http://www.prlog.org/11410027-hdl-design-house-adopts-magmas-full-suite-of-software-to-accelerate-soc-and-ip-development.html

Magma Design Automation is the latest member of DFMC

August 29th, 2010

The Silicon Integration Initiative (Si2) accepts Magma Design Automation as the latest member of the Design For Manufacturability Coalition (DFMC). Other semiconductor supply chain players who are members of the coalition include Cadence Design Systems, IBM, Intel, Mentor Graphics, STARC, Synopsys, Tela Innovations and Texas Instruments.

The group also reports that the DFMC members unanimously approved a 60-day Intellectual Property review period for the first official release of the specification for OpenDFM, a high-level DRC language that can be translated into a variety of proprietary verification languages with no loss of accuracy or performance. OpenDFM describes the patterns for physical verification at a higher level than traditional DRC rules and recent tests indicate it has the potential to reduce the volume of DRC rules by 10X-20X. It is scheduled for release later this year with rapid adoption expected by all major EDA vendors, silicon foundries, and end-user companies.

The next release of OpenDFM will add rules for lithography, chemical mechanical planarisation and critical area analysis. OpenDFM provides a compact notation for the description of the patterns of physical verification rules that include conditional rules and ranges of acceptable values.

DFMC’s charter is to specify open standards for software interfaces between EDA software tools and manufacturing software. The specification includes standard terminology definitions, semantics and exchange formats for relevant manufacturing information. It also includes standard software API for models describing different manufacturing processes, yield mechanisms and circuit behaviours.

“The DFMC is producing important work for the industry and we are pleased to have all major EDA vendors united in this important effort,” said Steve Schulz, president and CEO, Si2.

By joining DFMC, Magma continues to support the industry-wide initiative towards developing a common runset language. “With increasing design rule complexity and number of rules at 65 nm and below, physical verification can become a bottleneck in the delivery schedule,” said Anirudh Devgan, general manager of the custom design business unit of Magma. “Our collaboration with other members of the DFMC to define the specification and ensure interoperability of Quartz DRC and Quartz LVS with OpenDFM demonstrates our commitment to providing designers with faster physical verification flows.”

Membership in the DFMC is open to all interested parties across the semiconductor supply chain.

Source:http://www.eetindia.co.in/ART_8800618159_1800000_NT_4766950f.HTM

Magma Announces Quartz iPOP Initiative

August 26th, 2010

Magma Announces Quartz iPOP Initiative – Delivers “improved Productivity, Operability and Performance” for Faster, Higher Capacity Physical Verification

Program Offers New Licensing Model to improve Return On Investment for Physical Verification Flows

Bangalore (OPENPRESS) August 26, 2010 — Magma® Design Automation Inc. (Nasdaq: LAVA), a provider of chip design software, today launched Quartz iPOP, the “improved Productivity, Operability and Performance” initiative to facilitate designers’ adoption of the Quartz™ DRC and Quartz LVS software for designs targeted at 65 nanometers (nm) and below. Magma’s Quartz products, the first truly scalable physical verification solutions, handle larger designs and provide turnaround time up to an order of magnitude faster than traditional solutions – without sacrificing accuracy or requiring additional hardware. These unique capabilities provide the improved productivity and performance necessary to cope with the higher verification burden for designs at 65 nm and smaller without increasing the physical verification budget.

“The proportion of design activity at smaller geometries continues to increase. Just to maintain the same level of productivity means the physical verification needs to get faster,” said Anirudh Devgan, general manager of Magma’s Custom Design Business Unit. “Because the Quartz line is the only set of products that is fully scalable, it’s the best verification option as design geometries shrink.”

Foundry Report: 40-nm Wafer Shipments up 30 Percent
In its second quarter 2010 earnings report, TSMC revealed that 43 percent of its revenue comes from its 65- and 40-nm process nodes, and the number of 40-nm wafer shipments increased by 30 percent over the previous quarter. The adoption rate of advanced process nodes is accelerating, and many wireless, networking, graphics and other high-volume semiconductor companies have already migrated to 65-nm and smaller process technologies.

Faster, Higher Capacity Physical Verification Required at 65-nm and Below
The number of transistors that can be placed on an integrated circuit doubles approximately every 2 years – consistent with the predictions of Moore’s Law. At 65 nm and below, the rule complexity and number of rules increase significantly. As a result, the cost of hardware and software, along with the runtime required for physical verification may quadruple as customers move to each new process node. At 65 nm and below, traditional physical verification solutions fail to meet capacity, turnaround time and accuracy requirements.

“At 65-nm and below, IC size and design rule complexity make physical verification an even tougher, time-consuming challenge – frequently pushing chip delivery past acceptable deadlines,” Devgan said. “With easy access to Quartz DRC and Quartz LVS through the Quartz iPOP program, designers targeting 65-nm and smaller processes can experience firsthand the tremendous time- and cost-saving advantages of the industry’s fastest, fully scalable physical verification solution.”

Quartz iPOP: Better ROI, New Licensing Model and Free Trial of Quartz DRC and Quartz LVS
The iPOP program is designed to demonstrate the superior productivity and performance delivered by Magma’s Quartz DRC, Quartz LVS and Talus® qDRC physical verification solutions, and to ease adoption of the Quartz product the iPOP program features a new licensing model that enables designers to increase the return on investment (ROI) in Magma’s physical verification tools.

The Quartz products have been proven to provide sign-off quality results across a wide range of customers, design styles and process nodes. Quartz DRC and Quartz LVS enjoy broad foundry support and can be used for sign-off or in conjunction with third-party physical verification tools. Users of Magma’s Talus IC implementation system can achieve additional improvements in turnaround time and predictability with Talus qDRC, which provides Sign-off in the Loop™ physical verification. Unlike traditional tools, Talus qDRC runs during placement and routing to immediately identify and correct design rule violations, allowing Talus to generate sign-off-clean designs.

In addition to a new licensing model, the iPOP program features a free trial of the Quartz DRC and Quartz LVS software and an online quiz that lets designers demonstrate their knowledge of physical verification and enter into a monthly drawing for an Apple iPad. Designers can request the Quartz software evaluation and take the quiz by visiting www.magma-da.com/QuartziPOP. Only current and prospective Magma customers are eligible to win. No purchase necessary to enter, play or win. A purchase will not improve chances of winning.

Source:http://www.theopenpress.com/index.php?a=press&id=81907

Magma Design Automation to hire more, 5 products in pipeline

April 8th, 2010

US headquartered Magma Design Automation, provider of chip deisgn software, said that it had five additional products in the pipeline

and was looking at increasing its head count by hiring 40-50 persons globally next fiscal starting May.

“We will be hiring 40-50 persons next fiscal”, Rajeev Madhavan, CEO and Chairman of the Board told PTI.

The firm currently has 700 headcount globally with 200 in India spread over three cities — Bangalore, Mumbai, Delhi.

It has also recently announced appointment of Alok Mehrotra, as Managing Director, Magma India.

Magma Design Automation develops software for electronic design automation (EDA), enabling integrated circuit designers to meet critical time-to-market objectives, improve chip performance and handle multimillion-gate designs.

Magma’s EDA software was used to create complex, high-performance integrated circuits (ICs) for cellular telephones, electronic games, WiFi, MP3 players, DVD/digital video, networking, automotive electronics and other electronic applications, he said.

Coming out of the recession, the firm was now looking at launching new products that would enable to do more with less people. “We are building in and getting confident about our technology”, he said.

“The last three-four quarters have been good for us. We are bullish and we are keen in getting our differentiated tools out”, he said.

With the changing scenario in India, he said it was now imperative not to have products just launched in the US but to have launches from here to ensure deployment and adoption.

“We are planning to have India as a launch pad for new things.

Source:http://economictimes.indiatimes.com/news/news-by-industry/jobs/Magma-Design-Automation-to-hire-more-5-products-in-pipeline/articleshow/5773696.cms

Magma announces agenda for music India users conference

March 18th, 2010

Magma Design Automation Inc. (Nasdaq: LAVA), a provider of chip design software, today announced the final agenda for the MUSIC India users conference in Bangalore on March 30. The program will feature technical presentations given by Magma users and design industry experts. Magma CEO Rajeev Madhavan will deliver a keynote address entitled The Electronic Ocean.

MUSIC Agenda Focuses on Meeting Todays Analog and Digital Design Challenges

MUSIC provides an open forum for users to gain expertise using Magmas chip design software, and to exchange ideas about and solutions for the challenges of analog and digital integrated circuits and system-on-chip (SoC) designs.

Over the years MUSIC has become a leading venue for Magma users to gather, share and learn best practices and solutions. This years program covers a range of Magma software capabilities including library characterization, synthesis, placement and routing, floor planning, power optimization and circuit simulation. Users will share useful tips on how to leverage Magma software to improve results, reduce power, minimize costs and increase productivity.

User presentations will include: A Solution to Power Optimization using the Magma UPF Flow Evaluation of SiliconSmart Library Modeling for Accurate and IR-Drop-Aware Timing Analysis Optimal Design Methods for Multi-Voltage Domain, Multimillion-Gate SoCs using Talus Honey, I Shrunk the TAT!! – Implementation of an Extremely Schedule-Critical 45 nm, Multimillion-Gate SoC using Talus 1.1 Early and Efficient Decap and Automatic Power Metal Fill Insertion using Talus Magma FineSim Simulation Verification and Performance for Mixed-Signal/Analog Blocks in Complex SoC Designs A Convergent Routing Methodology for High-Performance Designs Predictable Timing Closure for Hierarchical Designs using the Talus Flow Manager Talus Vortex 1.1s Enhanced Router for 28 nm Case Study of Efficient Design Closure Methodologies in a Timing-Critical and Highly Congested Multicore, Complex SoC A Minimum-Pulse-Width Measurement Methodology

Source:http://www.webnewswire.com/node/515577

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