Lattice Semiconductor Corp. (LSCC) has unleashed its Lattice Diamond 1.4 software that the company says is ideal for Lattice FPGA products. The design software boasts usability enhancements that make FPGA design exploration easier and cuts time to market, added the company.
The Lattice Diamond 1.4 software enhances support for the MachXO2 PLD family by providing final production timing, power models and bit-streams for the entire family. This includes the latest wafer-level chip scale packaged version of the LCMXO2-2000U and LCMXO2-1200U devices that are geared for very high volume, cost- and power-sensitive applications. Moreover, customers can begin designing with the low cost, low power mid-range LatticeECP4 FPGA family, noted LSCC.
The design environment enables users to easily explore design alternatives as they target the type of applications ideally suited for the MachXO2 PLD family. Lattice Diamond 1.4 software includes final data for timing, power, package and bitstream based on the actual silicon characterization of all the MachXO2 devices, stated the company. The final simultaneous switching output (SSO) data is available for all packages (except the wafer-level chip scale package of the LCMXO2-2000U).
Lattice Diamond 1.4 software provides a report of device resources used by level of design hierarchy following either the synthesis or the map step (a process that maps the synthesis output to the device resources). Device resources can therefore be reported out as both logical (registers) and physical (slices) elements. This feature helps users quickly understand what parts of their design are using scarce device resources so that they can optimize the design for the targeted device. This information can be exported to a text or a CSV file to enable analysis in other tools.
To improve timing closure productivity, users can now set up the multiPAR placement and routing tool to stop after either trying a maximum number of seeds (or starting points) or when the last seed run has resulted in timing closure—whichever comes first. In order to perform design exploration even faster, these multiPAR tasks can now be distributed to run in parallel on computers with a multicore CPU.
In addition, users can employ the Run Manager tool to process multiple implementations (or design structures) in parallel and accelerate timing and utilization results for these multiple implementations. Users can individually control the maximum number of implementations and multiPAR processes that can be run simultaneously. With Lattice Diamond 1.4, LSCC stated that users can also compare run reports of multiple implementations side by side and easily determine the best implementation for their design.
Lattice Diamond 1.4 software also aids users who want to migrate their designs later to a lower cost device within the same device family while preserving the existing board layout. This capability has now been extended to all the Lattice device families supported by Lattice Diamond software.
Ease of Use
Lattice Diamond software is an intuitive user design environment that enables users to complete their design more quickly, touted the company. The pin assignment Design Rule Check (DRC) engine has been redesigned and implemented for the LatticeECP3, MachXO2 and LatticeSC device families to provide real-time as well as on-demand DRC during pin assignment and configuration, and a user-friendly report that helps identify and correct pin usage issues, continued LSCC.
In addition, users of the Lattice Synthesis Engine (LSE) tool can now create and edit Synopsys Design Compiler (SDC) synthesis constraints in the Lattice Design Constraints graphical editor. The editor automatically populates design clock, port and net names and provides real time syntax and semantic checks. It generates an SDC file that can be used with LSE.
Included with this release is the new Diamond Deployment Tool. It uses an intuitive wizard approach to create the appropriate device programming file in the format required by the user’s deployment method. Along with Diamond Programmer, the tools include features of ispVM System software, but with a more intuitive workflow.
Lattice Diamond software incorporates Synopsys’ Synplify Pro advanced FPGA synthesis for Windows and Linux. Aldec’s Active-HDL Lattice Edition II simulator is also included for Windows. In addition to the tool support for Lattice devices provided by the OEM versions of Synplify Pro and Active-HDL, Lattice devices are also available in the full versions of Synopsys Synplify Pro and Aldec Active-HDL. Mentor Graphics ModelSim SE and Precision RTL synthesis also support Lattice devices.
Lattice Diamond 1.4 software is available for download for both Windows and Linux. Once downloaded and installed, the software can be used with either the Lattice Diamond free license or the Lattice Diamond subscription license. The Lattice Diamond free license can be immediately generated upon request from the Lattice website and provides no cost access to many popular Lattice devices such as the MachXO2 and MachXO device families, the LatticeXP2 and LatticeECP2 FPGA families as well as the Platform Manager devices. The Lattice Diamond free license enables Synopsys Synplify Pro for Lattice synthesis as well as the Aldec Lattice Edition II mixed language simulator.